This invention relates to semiconductor chips having a mesa structure, and particularly to the manufacture of such chips using a mechanical sawing process.
It is known to provide semiconductor chips, particularly for rectifier devices, in the form of a generally flat semiconductor substrate having a mesa extending upwardly from the substrate. A p-n junction within the mesa intercepts the sloped walls of the mesa, with the result being that electric fields adjoining the p-n junction have lower strengths at the mesa surfaces than within the mesa. Thus, upon conditions giving rise to voltage breakdown of the device, the breakdown occurs within the mesa rather than along the mesa surfaces. As known, such internal breakdowns are much less destructive than breakdowns along the surfaces, and, by avoiding surface breakdowns, the device can withstand much higher energy pulses before being destroyed.
The theory concerning surface voltage breakdown was perhaps first described and analyzed by R. L. Davies and F. E. Gentry in "Control of Electric Field at the Surface of P-N Junctions", IEEE Transactions on Electron Devices, July, 1964, pp. 313-323. In the devices experimented with by the authors, sloped mesa walls were obtained by grinding. More typically, in recent times, sloped mesas are obtained by anisotropical etching, as described, for example, in U.S. Pat. Nos. 4,740,477, 4,891,685, 5,010,023 and 5,399,901, all issued to W. G. Einthoven et al. (The subject matter of these patents is incorporated herein by reference.) Such anisotropical etching processes comprise providing a silicon wafer coated with a masking layer of silicon nitride, applying a photoresist layer over the masking layer, and forming a mesa defining pattern in the photoresist using a photomask. Etching is then performed through the patterned photoresist layer and into the underlying masking layer and wafer for defining a plurality of mesas on the wafer surface. Having defined the mesas, subsequent processing steps can be performed for further defining the parameters of each mesa containing chip to be formed. Then, the mesa side walls are oxidized for passivating the mesa wall surfaces. The masking layers overlying the mesas are removed (typically in a photolithographic process using a photomask) for exposing silicon surfaces at the mesa tops, the exposed surfaces and wafer bottom surface are metal plated for forming chip electrodes, and the thus basically completed chip structures are separated in a wafer-dicing operation, e.g., by mechanical sawing.
While the foregoing described process is quite satisfactory and is extensively used, the process is relatively expensive owing to the need for relatively complicated processes, e.g., the preparation and use of photomasks in the process, and the costs of the materials used. The question was thus raised by the inventors herein whether less expensive mesa shaping processes could be used. Mechanical sawing, already known for dicing the substantially completed wafer, was considered for the earlier step of forming the mesas and, as hereinafter described, was adopted as part of a chip fabricating process.
As just noted, mechanical sawing for dicing wafers is known. Also, while such sawing is typically done only after substantially all the processing required for the individual chips is completed, there are instances where the sawing process used to dice the wafer into chips is also used to shape and passivate the sides of each chip.
In the U.S. Pat. No. 4,904,610, to Shyr, for example, it is explained (at column 4, lines 23 and 24) that the wafer dicing, performed by sawing, results in "a beveled groove" (the groove being sawed entirely through the wafer and thus shaping the sides of each chip) "yielding a high breakdown voltage for a rectifier or other end product."
More specifically, in the process shown in the Shyr patent, a silicon semiconductor wafer, substantially completely processed and including metal electrodes on opposite major surfaces, is adhered, via a wax layer, to a rigid support substrate. A plurality of orthogonal grooves having sloped side surfaces are then sawed entirely through the thickness of the wafer and partly into the underlying wax layer. An etching process is used to smooth the groove sawed surfaces, and a silicon resin is then deposited onto the grooved surface of the wafer for filling in the grooves. The resin, after curing, adheres strongly to the groove walls but only poorly to the metal plated surface of the wafer. The resin is then readily removed, as by buffing, from the wafer plated surface without removal of the resin from within the grooves. The wafer is then separated from the supporting substrate. Although the wafer has been sawed through into separate chips, the chips remain attached to one another by the cured resin between and attached to the chips. Solder is then selectively applied to the surfaces of the metal electrodes on the chips, and the chips are finally separated by slicing through the resin layers between the chips. The side surfaces of the chips remain coated with the cured resin which serves to passivate the chip sides.
Now, while the Shyr process does result in chips having passivated, sloped side surfaces for high voltage breakdown characteristics, the Shyr process is basically a variation on known wafer dicing processes typically performed after all the basic processing of the precursor chips has been completed. Specifically, at the stage of wafer production when the Shyr dicing process is performed, all high temperature processing of the precursor chips has been completed and further high temperature processing is avoided. Thus, in the Shyr process, the metal electrodes (preferably provided in a high temperature processing step, i.e., in excess of 400.degree. C.) are already present, and the chip passivating material used, i.e., the disclosed silicone resin, is applied and cured at lower temperatures, e.g., around 200.degree. C.
Conversely, as above-explained, and as described hereinafter, the present invention involves the use of mechanical sawing as a direct substitution for the previously used anisotropic etching process and at a relatively early part of the chip fabrication schedule. Nothing in Shyr shows nor suggests such direct substitution or how it could be accomplished.
The use of "mechanical cutting" for forming mesas is also disclosed in the afore-cited U.S. Pat. Nos. 4,740,477 and 4,891,685 to Einthoven (an inventor herein). However, to the knowledge of the inventors herein, all devices made in accordance with these patents employ anisotropic etching for forming the mesas. "Mechanical cutting", i.e., sawing, has never actually been used nor considered in detail until the making of the present invention. Also, such "actual" devices are made using photolithographic processes both for forming the mesas and for providing metal electrodes on the tops of the mesas. Such photolithographic processes are expensive to perform. As described hereinafter, the present invention provides for formation of the mesas, the passivation of the mesa side walls, and the metallizing of the mesa top surfaces all without the use of photolithographic processes.